1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same.
2. Description of Related Art
In recent years, in accordance with the progress in the performance of semiconductor devices, a technique for forming an insulating film, so-called “low-k film (low dielectric constant insulating film)” having a lower relative dielectric constant than SiO2 has come to be used in a semiconductor device production process. Being available in a great variety of types, a “low-k film” generally has poor adherence and low mechanical strength. Accordingly, there has been a problem that the spread of film detachment and cracks that occur during a wafer dicing process cannot be prevented.
FIGS. 26A and 26B are drawings illustrating a seal ring structure of a related art. A seal ring, which is a bulkhead provided along the periphery of a semiconductor chip in order to prevent moisture from getting into a low dielectric constant film, is generally formed by a wiring layer. FIG. 26A is a lateral plan view of a semiconductor device 10, while FIG. 26B is a vertical front view of the semiconductor device 10. FIG. 26B corresponds to a cross-sectional view taken along the line H-H′ of FIG. 26B.
The semiconductor device 10 has a structure in which a substrate 12, such as a silicon substrate, a lower layer insulating film 14, such as a SiO2 film, and an interlayer insulating film 16 containing a low dielectric constant film are stacked together in this order. In the drawing, the left side of the broken line is a chip interior, while the right side of the broken line is a seal ring part. There is a dicing line (not shown in the drawing) on a further outer circumference of the seal ring part. In the chip interior which is an element-forming region, a wiring layer 32 and a via layer 30 are alternately formed in this order in the interlayer insulating film 16. In the seal ring part, a W seal ring 34 is formed in the lower-layer insulating film 14, while a wiring layer 24 and a via layer 22 are alternately formed in this order in the interlayer insulating film 16. The wiring layer 24 and the via layer 22 are formed in the same layer as the wiring layer 32 and the via layer 30 in the chip interior, respectively. Furthermore, each wiring and each via are formed of a barrier metal film 18 and a copper-containing metal film 20.
However, in such a configuration, if a crack or film detachment 40 occurs from the dicing line side located in the right side of the drawing, there has been a problem in which such a crack or film detachment 40 propagates to the inside through a part between the via and the wiring, and then develops into a crack or film detachment in the chip interior.
Patent document 1 (Japanese Patent Application Publication No. 2006-5011) discloses a configuration in which multiple isolated pockets of insulating material are formed in a wide seal ring wiring. The document discloses a configuration having such an arrangement in which the occurrence of dishing and erosion in the wide seal ring wiring during CMP in the formation of wirings is prevented, and therefore the possibility of the occurrence of short circuit among wirings is eliminated.
Patent document 2 (Japanese Patent Application Publication No. 2005-167198) discloses a seal ring configuration in which a continuous seal via is arranged in an interlayer insulating film provided with a via and a wiring forming a dual damascene wiring. By employing this configuration having less junctions in the seal ring part, it is possible to more effectively prevent the invasion of impurities and the like through a junction compared to a configuration having more junctions; therefore, such a configuration is considered to be able to provide a strong seal ring structure.
[Patent document 1] Japanese Patent Application Publication No. 2006-5011
[Patent document 2] Japanese Patent Application Publication No. 2005-167198
However, in the art disclosed in Patent document 1, a via layer and a wiring layer in the seal ring part are alternately formed at the same height as a via layer and a wiring layer in an element forming layer; therefore, junctions in the seal ring are located at the same height as interfaces of the surrounding insulating films. Hence, no solution is provided to the problem in which detachment and cracks from the outer circumference are to spread into the interior.
In the meantime, in the art disclosed in Patent document 2, the number of junctions is reduced. However, junctions in the seal ring are arranged to be at the same height as junctions between wirings and vias in the chip region, and also to be at the same height of interfaces of the surrounding insulating films. Accordingly, in the case where film detachment occurs, there is still a problem of detachment and cracks spreading from the outer circumference to the junction of the seal ring and then also into the interior.